Fabrication Process of a Semiconductor Device Having a Capacitor

ABSTRACT

A method of manufacturing a semiconductor device includes forming a first trench in a capacitor device region of a semiconductor substrate, forming a capacitor insulation film over a sidewall surface of the first trench, forming a semiconductor film to cover the first trench, a resistor device region of the semiconductor substrate and a logic device region of the semiconductor substrate, introducing a first impurity element into the semiconductor film formed over the first trench, patterning the semiconductor film to form a top electrode in the capacitor device region, a resistor in the resistor device region and a gate electrode in the logic device region, annealing the semiconductor substrate, and introducing a second impurity element in the resistor.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is based on Japanese priority application No.2007-265838 filed on Oct. 11, 2007, the entire contents of which arehereby incorporated by reference.

BACKGROUND OF THE INVENTION

The present invention generally relates to semiconductor devices andmore particularly to the fabrication process of a semiconductor devicein which a capacitor and a resistor are integrated.

Conventionally, semiconductor devices are used in which semiconductordevice elements such as transistors are integrated on a semiconductorsubstrate together with capacitors and resistors. With suchsemiconductor devices, the capacitors are formed by utilizing trenchesformed in the semiconductor substrate, while the resistors are formed asa polysilicon pattern on the semiconductor substrate.

With the capacitor of the type thus formed by using the trench formed atthe surface of the semiconductor substrate, an oxide film is formed onthe trench surface as a capacitor insulation film, and a polysiliconpattern is formed as a top electrode such that the polysilicon patternfills the trench via the oxide film. With the capacitor of such aconstruction, there is a need for providing high conductivity to thepolysilicon pattern filling the trench by doping with an impurityelement to high concentration level up to the part filling the trenchbottom.

SUMMARY OF THE INVENTION

In an aspect, a method of manufacturing a semiconductor device hasforming a first trench in a capacitor device region of a semiconductorsubstrate, forming a capacitor insulation film over a sidewall surfaceof the first trench, forming a semiconductor film over the first trench,a resistor device region of the semiconductor substrate and a logicdevice region of the semiconductor substrate, introducing a firstimpurity element into the semiconductor film over the first trench,patterning the semiconductor film to form a top electrode in thecapacitor device region, a resistor in the resistor device region and agate electrode in the logic device region, annealing the semiconductorsubstrate, and then introducing a second impurity element in saidresistor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1F are diagrams showing the process of fabricating asemiconductor device according to a related art of the presentinvention;

FIG. 2 is a diagram explaining the problems in the semiconductor devicefabricated with the process of FIGS. 1A-1F;

FIG. 3 is a diagram explaining the effect of diffusion of an impurityelement caused by a thermal annealing process;

FIGS. 4A and 4B are diagrams showing the change of resistance valuecaused with the thermal annealing process;

FIGS. 5A-5C are diagrams showing a relationship between a variation of aresistance change and the product of the length and width of a patternarea according to the present invention;

FIG. 6 is a diagram showing the specimen used with the experiments ofFIGS. 5A-5C;

FIG. 7 is a diagram showing the cause of the variation of resistancevalue;

FIGS. 8A-8K are diagrams showing the process of fabricating asemiconductor device according to a first embodiment of the presentinvention;

FIGS. 9A-9K are diagrams showing the process of fabricating asemiconductor device according to a second embodiment of the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIGS. 1A-1F show the process of forming a capacitor in a semiconductordevice according to a related art of the present invention.

Referring to FIG. 1A, there is formed an isolation trench 11B in asilicon substrate simultaneously to formation of a device isolationtrench 11A, and the device isolation trench 11A is filled with a deviceisolation insulation film 11I of SiO₂ in the step of FIG. 1B. At thesame time, the trench 11B is filled with an insulation film 11J also ofSiO₂.

Further, in the step of FIG. 1C, the device isolation insulation film11I is covered with a resist pattern R, and the insulation film 11J inthe trench 11B is receded by conducting a wet etching process. Furtherin the step of FIG. 1D, there is formed an insulation film 12 by athermal oxide film, for example, on the surface of the silicon substrate11 such that the insulation film 12 covers the exposed surface of thetrench 11B.

Further, in the step of FIG. 1E, there is deposited a polysilicon film13 on the structure of FIG. 1D to fill the trench 11B.

With such a formation process of the capacitor, it is advantageous toform the insulation film 12 by the same insulation film that constitutesthe gate insulation film of the semiconductor element (p-channelmetal-oxide semiconductor (MOS) transistor or n-channel MOS transistor)formed on the device region (not shown), which is defined on the samesemiconductor substrate 11 by the device isolation region 11I, for thepurpose of reducing the number of process steps. Further, for thepurpose of reducing the number of process steps, it is also advantageousto form the polysilicon top electrode 13 by the same polysilicon layerconstituting the gate electrode of the transistor.

Meanwhile, with the highly miniaturized semiconductor devices in currentuse, it is practiced in the art, for purposes of facilitating thresholdcontrol, that the gate electrode of a p-channel MOS transistor formed ona semiconductor substrate is formed of a p-type polysilicon electrodeand the gate electrode of an n-channel MOS transistor formed on the samesemiconductor substrate is formed of an n-type polysilicon electrode.Thus, in the step of FIG. 1E, the polysilicon film 13 is generallyformed in an undoped state, and the undoped polysilicon film thusdeposited is doped later to n-type in the device region of the n-channelMOS transistor and to p-type in the device region of the p-channel MOStransistor by way of ion implantation process.

Thus, in the state of FIG. 1E, the polysilicon film 13 does not havesubstantial conductivity, and the conductivity is given in the step ofFIG. 1F by introducing a dopant that causes fast diffusion, such asboron ions (B+), by way of ion implantation process.

Conventionally, it has been shown, with the capacitors of such aconstruction, that a capacitance of 1.5 fF is attained in the case of adevice generation of a 0.25 μm design rule, where the trench 11B has awidth of 0.25 μm.

With the semiconductor devices of the generation of furtherminiaturization, and thus of a more strict design rule, on the otherhand, there is a need of increasing the depth of the trench 11B tocompensate for a decrease of capacitance caused by miniaturization ofthe capacitors. Thus, there is a need of increasing the depth of thetrench 11B to about 0.3 μm, for example, with the generation that usesthe design rule of 0.1 μm, in which the width of the trench 11B is 0.1μm.

On the other hand, the inventor of the present invention has discovered,in the investigations that constitute the foundation of the presentinvention, that there arises a situation that even a boron (B) dopant,which is known to have a relatively large diffusion coefficient, cannotreach the part of the polysilicon film filling the trench 11Bsubstantially, and as a result, there arises depletion in the part ofthe polysilicon film 13 encircled in FIG. 2. In this investigation, itshould be noted that experiments and simulations were conducted withregard to the ion implantation process of FIG. 1F while changing theacceleration energy and dose variously. Because of a lack ofconductivity in such a part, the polysilicon film 13 cannot function asthe effective top electrode of capacitor. This means that it is notpossible to compensate for the decrease of capacitance associated withdevice miniaturization, even when the depth of the trench 11B isincreased.

Thus, in order to solve the problem of depletion of the polysilicon film13 filling the trenches 11B in the capacitor formed in such trenches11B, the inventor of the present invention has conducted experiments, inthe investigations that constitute the foundation of the presentinvention, by annealing the structure of FIG. 2 under variousconditions.

In the experiments, there is formed a trench in a silicon substrate 11with an n+ type well with an edge length of 0.1 μm and a depth of 0.3μm, and an SiO₂ film was formed on the surface thereof as the ainsulation film 12 with a film thickness of about 4 nm. Further, anundoped polysilicon film was deposited thereon as the polysilicon film13 as shown in FIG. 2, and the ion implantation process of B wasconducted under the acceleration voltage of 4 keV with a dose of5.5×10¹⁵ cm².

The structure thus obtained was then annealed under the followingvarious conditions:

in Experiment A, no annealing was made (Comparative Reference);

in Experiment B, annealing was conducted for 3 seconds at 1000° C. in anitrogen gas ambient;

in Experiment C, annealing was conducted for 0 seconds (only temperaturerising and lowering were made, zero holding time) at 1050° C. in anitrogen gas ambient;

in Experiment D, annealing was conducted for 3 seconds at 1025° C. in anitrogen gas ambient;

in Experiment E, annealing was conducted for 3 seconds at 1025° C. in anitrogen gas ambient;

in Experiment F, annealing was conducted for 10 seconds at 1000° C. in anitrogen gas ambient; and

in Experiment G, annealing was conducted for 3 seconds at 1050° C. in anitrogen gas ambient.

FIG. 3 shows the change of capacitance of the capacitors caused as aresult of such thermal annealing processes with regard to theComparative Example.

Referring to FIG. 3, it can be seen that, in the Experiment Acorresponding to the Comparative Reference, there is realized thecapacitance value of about 0.95 fF, while FIG. 3 indicates that thiscapacitance value can be increased by conducting thermal annealingprocess. Particularly, with the specimens of the Experiments D, E, F andG, it can be seen that there is attained an increase of capacitancevalue of more than 60% as compared with the resistance value of theComparative Reference. Thus, with these specimens, practical capacitancevalues were attained Obviously, this has been the result that B atomsintroduced into the polysilicon film 13 reach the part near the bottomof the trench 13 by diffusion which is caused by the thermal annealingprocess. As a result, the problem of depletion is eliminated or reducedand the polysilicon film 13 has uniform conductivity.

Thus, it has been confirmed that the problem of depletion can beresolved successfully even in the capacitors formed in the trenches withlarge aspect ratios as shown in FIG. 2, by performing the thermalannealing process.

On the other hand, the inventor of the present invention has discoveredthat, in the case where resistor patterns are formed over the siliconsubstrate 11 by the polysilicon film 13, a variation of resistance valueis induced for these resistor patterns when such thermal annealingprocess is conducted. The discovery of this problem leads to the concernthat normal operation may not be attained with such semiconductordevices.

FIGS. 4A and 4B show the distribution and variation of the resistancevalues obtained for the specimens of the Experiments A-G of FIG. 3.

In the experiments shown in FIGS. 4A and 4B, it should be noted that B(boron) is introduced into the polysilicon film 13 formed on the siliconsubstrate under the acceleration voltage of 8 keV with a dose of4.5×10¹⁵ cm⁻².

Referring to FIGS. 4A and 4B, it can be seen that there is not only anincrease of resistance value but also an increase of variation of theresistance values in the specimens subjected to the thermal annealingprocess, as compared with the case of Comparative Reference A.

For example, it can be seen that the resistance value of about 4.6 kΩobtained for the Comparative Reference has increased to 6.7 kΩ with thespecimen of the experiment G as a result of the thermal annealingprocess. Associated therewith, the variation of the resistance isincreased, in terms of the 2σ value, from +/−1% or less for the case ofthe Comparative Reference A to +/−4% for the case of the Experiment G.

It is believed that such a change of resistance value of the polysiliconpattern is caused by an escape of B from the polysilicon film as aresult of the thermal annealing process.

It is believed that a similar variation of resistance value would beinduced in the polysilicon gate electrode patterns of the p-channel MOStransistors, which are doped with B.

Thus, in a first aspect, an embodiment of the present invention providesa method for fabricating a semiconductor device that includes the stepsof: forming a first trench part in a capacitor device region of asemiconductor substrate, forming a capacitor insulation film on asidewall surface of the first trench part, forming a semiconductor filmso as to cover the first trench part, a resistor device region of thesemiconductor substrate and a logic device region of the semiconductorsubstrate, introducing a first impurity element into the semiconductorfilm in a part over the first trench part, patterning the semiconductorfilm to form a top electrode pattern in the capacitor device region, aresistor pattern in the resistor device region and a gate electrodepattern in the logic device region, annealing the semiconductorsubstrate, and then introducing a second impurity element in saidresistor pattern.

In another aspect, an embodiment of the present invention provides amethod for fabricating a semiconductor device that includes the stepsof: forming a first trench part in a capacitor device region of asemiconductor substrate, forming a capacitor insulation film on asidewall surface of the first trench part, depositing a semiconductorfilm so as to cover the first trench part, a resistor device region ofthe semiconductor substrate and a logic device region of thesemiconductor substrate, introducing a first impurity element into thesemiconductor film, annealing said semiconductor substrate, patterningthe semiconductor film to form a top electrode pattern in the capacitordevice region, a resistor pattern in the resistor device region and agate electrode pattern in the logic device region, and introducing asecond impurity element in the resistor pattern.

According to the embodiment of the present invention, it becomespossible, in the semiconductor devices having a trench part for thecapacitor device region, to dope an amorphous silicon film or apolysilicon film formed so as to fill the trench part, with an impurityelement with a high concentration level up to the part covering thebottom part of the trench part, by conducting a thermal annealingprocess, even in the case where the semiconductor device is a highlyminiaturized semiconductor device and the trench part of the capacitordevice region has a large aspect ratio.

Further, according to the embodiment of the present invention, itbecomes possible to effectively compensate for the decrease ofcapacitance value of the capacitors as in the case of the semiconductordevice of the related art as a result of escape from the polysilicon topelectrode pattern.

Thereby, the problem of the escape of the impurity element from theresistor patterns of amorphous silicon or polysilicon previously, causedby such a thermal annealing process, can be effectively avoided, bycarrying out the process of introducing the second impurity element intothe amorphous silicon or polysilicon resistor pattern after conductingthe thermal annealing process. As a result, the problem of the variationof the polysilicon resistor patterns formed in the resistor deviceregion after the thermal annealing process is suppressed effectively.

Particularly, by carrying out the patterning process of the resistorpattern of amorphous silicon or polysilicon before conducting thethermal annealing process, the patterning process to the amorphoussilicon film or polysilicon film is conducted in the state in whichcrystal grain growth is not yet caused in the amorphous silicon film orthe polysilicon film. Thereby, it becomes possible to carry out thepatterning while using a dry etching recipe, which is used forpatterning ordinary amorphous silicon films or polysilicon films.

FIG. 5A corresponds to the related art of the present invention andrepresents the variation a of the resistance change ΔR, which has beencaused between a pair of mutually adjacent polysilicon patterns in thestructure shown in FIG. 6 in which a large number of polysiliconpatterns are formed side by side, each with a width W and a length L. InFIG. 5A, the vertical axis represents the variation σ, while thehorizontal axis represents the inverse of the root of the pattern areaL·W (1/SQRT(L·W)). Here, it should be noted that the variation σrepresents the variation of the resistance change ΔR as normalized tothe average resistance R (ΔR/R). In the specimen of FIG. 6, for example,the normalized resistance change ΔR/R is calculated, for the patternhaving the resistance value R1 and the adjacent pattern having theresistance value R2, as ΔR/R=(R1−R2)/{½(R1+R2)}.

In FIG. 5A, it should be noted that the smaller the value of thehorizontal axis becomes, the larger the area of the resistor patternbecomes. Likewise, the larger the value of the horizontal axis becomes,the smaller the area of the resistor pattern becomes.

It should be noted that, in the experiment of FIG. 6, a thermal oxidefilm is formed on the surface of a silicon substrate, followed byformation of an undoped polysilicon film by a chemical vapor deposition(CVD) process at the substrate temperature of 605° C. for the thicknessof 105 nm, and B+ is introduced thereafter by an ion implantationprocess under the acceleration voltage of 8 keV with a dose of 4.5×10¹⁵cm⁻².

There, the specimen indicated by solid squares represent the comparativereference, in which the polysilicon pattern thus obtained is notsubjected to a thermal annealing process except for the thermalannealing process conducted for activating the impurity element.

On the other hand, the specimen indicated by solid circles in FIG. 5Arepresent the specimen in which patterning was made to the polysiliconfilm to form the resistor patterns of FIG. 6 after the ion implantationprocess of B (boron), and further a thermal annealing process wasapplied thereafter at the temperature of 1000° C. for 10 seconds(corresponds to Specimen F of FIGS. 4A and 4B). There, the ionimplantation process was conducted under the condition as noted above.

Further, the specimen indicated by open circles in FIG. 5A represent thespecimen in which patterning was made to the polysilicon film to formthe resistor patterns of FIG. 6 after the ion implantation process of B(boron), followed further with a thermal annealing process at thetemperature of 1050° C. for 3 seconds (corresponds to Specimen G ofFIGS. 4A and 4B). Again, the ion implantation process was conductedunder the condition as noted above.

Referring to FIG. 5A, in the case the patterning of the polysiliconresistor patterns of FIG. 6 is made with a constant precision, a plotwas expected that would show a general tendency that the variation σ ofthe resistance value increases with increasing value of the horizontalaxis, and hence with decreasing pattern area. In fact, such a tendencycan be observed for some of the specimens represented by solid squares,solid circles and open circles.

On the other hand, with the specimen represented by solid squares andsolid circles, one can be also see that the specimen subjected to thethermal annealing process shows a tendency that the variation σ of theresistance value is larger than the variation of the comparativereference, in conformity with the relationship of FIG. 4B.

In FIG. 5B, the vertical axis and the horizontal axis are identical tothose of FIG. 4A and the same comparative reference specimen as in thecase of FIG. 5A are also represented by the solid squares.

In FIG. 5B, however, it should be noted that the solid circles representthe specimen in which the polysilicon film is first annealed at thetemperature of 1000° C. for 10 seconds, followed by introducing B+thereto by an ion implantation process under the same conditions as inthe case of FIG. 5A. Further, the patterning of the polysilicon film toform the resistor patterns of FIG. 6 was conducted thereafter.

Likewise, the open circles represent the experiments in which thepolysilicon film is first annealed at the temperature of 1050° C. for 3seconds, followed by introducing B+ thereto by an ion implantationprocess under the same conditions as in the case of the experiment ofFIG. 5A, and the patterning of the polysilicon film to the resistorpatterns of FIG. 6 is conducted thereafter.

Referring to FIG. 5B, it can be seen that the variation σ of theresistance value has become smaller compared with the variation of theresistance value of the comparative reference specimen. With thisspecimen, it should be noted that the ion implantation process wasconducted after the thermal annealing process at 1000° C. or 1050° C.

For example, with the specimen represented by solid circles, therelationship between a and 1/SQRT(L·W) is represented as y=1.8642× forthe case of the experiments of FIG. 5A, while in the experiments of FIG.5B, the foregoing relationship is represented by y=1.324×. Here, ycorresponds to the term σ and x corresponds to the term 1/SQRT(LW),

Further, in the example of the specimen represented by the open circles,the relationship between the term σ and the term 1/SQRT (LW) isrepresented as y=2.4767× for the case of the experiments of FIG. 5A,while in the case of the experiments of FIG. 5B, the foregoingrelationship is represented by y=1.1626×. Again, y corresponds to σ andx corresponds to 1/SQRT (LW). For the comparative reference specimenrepresented by the solid squares, the relationship between the term σand the term 1/SQRT (LW) is represented as y=1.3971× for any of FIGS. 5Aand 5S.

In FIG. 5C, the same vertical axis and the same horizontal axis are usedas in the case of FIGS. 5A and 5B, and the same comparative reference asin the case of FIGS. 5A and 5B are plotted similarly by the solidsquares.

Here, it should be noted that the solid circles represent the specimenin which the polysilicon film is patterned at first to form the resistorpatterns shown in FIG. 6, followed by a thermal annealing process at thetemperature of 1000° C. for 10 seconds, and ion implantation of B+ isconducted thereafter under the conditions similar to the experiments ofFIG. 5A. Further, the open circles represent the specimen in which thepolysilicon film is patterned at first to form the resistor patternsshown in FIG. 6, followed by a thermal annealing process at thetemperature of 1050° C. for 3 seconds, and ion implantation of B+ isconducted thereafter under the condition similar to the experiments ofFIG. 5A.

Referring to FIG. 5C, it can be seen that the variation σ of theresistance value has become smaller, in the specimen in which the ionimplantation process is conducted after the thermal annealing process at1000° C. or 1050° C., as compared with the comparative referencespecimen.

In the example of the specimen represented with the solid circles inFIG. 5C, the relationship between σ and 1/SQRT(L·W) is represented asy=1.8642×, wherein y corresponds to the term σ and x corresponds to theterm 1/SQRT(L·W), for the case of the experiments of FIG. 5A, while forthe experiments of FIG. 5C, the foregoing relationship is represented byy=1.2794×. Further, in the example of the specimen represented by theopen circles, the relationship between the term σ and the term1/SQRT(L·W) is represented as y=2.4767× in experiments of FIG. 5A, whilein the case of the experiments of FIG. 5C, the foregoing relationship isrepresented by y=1.3295×. With regard to the comparative referencespecimen represented by the solid squares, the relationship between theterm σ and the term 1/SQRT (L·W) is represented as y=1.3971× for any ofFIGS. 5A and 5C.

Thus, it can be seen that the variation σ of the resistance changebecomes smaller in the specimen in which the ion implantation processand patterning process are conducted after the thermal annealing processat 1000° C. or 1050° C., as compared with the variation of theresistance value for the comparative reference specimen.

FIG. 7 is a diagram showing the mechanism that causes the foregoingdifference of variation for the resistance value of the polysiliconresistor patterns between the case of the experiments of FIG. 5A and thecase of the experiments of FIG. 5B or FIG. 5C.

Referring to FIG. 7, it can be seen that there is formed a polysiliconresistor pattern 3 on the silicon substrate 1 over an insulation film 2of silicon oxide film, or the like, wherein there is an escape of theimpurity element. The impurity element has been introduced previouslyinto the polysilicon resistor pattern 3, when the polysilicon patternwas subjected to a thermal annealing process (RTA), as in the case ofthe thermal diffusion process explained with reference to FIG. 3. Suchescape of the impurity element from the polysilicon film appearsparticularly conspicuous for the case of using B for the impurityelement.

FIGS. 8A-8K are diagrams showing the process of fabricating asemiconductor device according to a first embodiment of the presentinvention.

Referring to FIG. 8A, there are defined a resistor device region 21A, acapacitor device region 21B and a logic device region 21C on a siliconsubstrate 21. A trench part 22A, a trench part 22B and a deviceisolation trench 22C are formed simultaneously, respectively, in theresistor device region 21A, the capacitor device region 21B and thelogic device region 21C.

In one example, the trench part 22B and the device isolation trench 22Care formed, in accordance with a design rule, such that the trench part22B and the device isolation trench 22C have a width of 0.08-0.25 μm atthe surface of the silicon substrate 21 and a depth of 0.2-0.35 μm.

The trench parts 22A and 22B and the device isolation trench 22C arefilled respectively with CVD oxide films 23A, 238 and 23C, whereinexcessive silicon oxide film at the surface of the silicon substrate 21is removed by chemical mechanical polishing (CMP) process.

Next, in the step of FIG. 8B, the resistor device region 21A and thelogic device region 21C are covered with a resist pattern (not shown),and an etch-back process is conducted to the exposed capacitor deviceregion 21B in order to etch back the silicon oxide film therein by a dryetching process. With this, the CVD oxide film 23B is receded at thetrench 22B until the CVD oxide film 23B is left at the bottom of thetrench 23B with a thickness of about 30-100 nm. Further, in this step,ion implantation of a p-type element such as B+, or if necessary ann-type element such as arsenic ions (As+) or phosphorous ions (P+), isconducted into the capacitor device region 21B, and width this, aconductive well 21W is formed as the bottom electrode of the capacitor.In the explanation below, illustration of the conductive well 21W willbe omitted.

Next, in the step of FIG. 8C, a thermal oxidation process is conductedto for the structure of FIG. 8B in an oxygen ambient at the temperatureof 1000° C., for example, and with this, a thermal oxide film 24 isformed on the surface of the silicon substrate 21 including the exposedsidewall surface of the trench part 22B with a thickness of 2 nm, forexample.

Next, in the step of FIG. 8D, an undoped polysilicon film 25 isdeposited on the structure of FIG. 8C at the substrate temperature of605° C. in order to fill the trench part 22B typically with thethickness of 105 nm. In place of the polysilicon film 25, it is alsopossible to deposit an amorphous silicon film. In this case, thesubstrate temperature is set for example to 530° C. in the depositionstep. Hereinafter, the film 25 will be designated as “silicon film”.

Next, in the step of FIG. 8E, there is formed a resist pattern R1exposing only the capacitor device region 21B on the structure of FIG.8D, and ion implantation of B+ is conducted into the silicon film 45while using the resist pattern R1 as a mask under the accelerationvoltage of 4 keV with the dose of 5.5×10¹⁵ cm⁻², for example. From theview point of the diffusion process to be explained later with referenceto FIG. 8G, it is preferable to use B+ having a large diffusioncoefficient for the impurity element in this step of FIG. 8E.

Next, in the step of FIG. 8F, the silicon film 25 of the structure ofFIG. 5E is patterned, and with this, there are formed resistor patterns25A in the resistor device region 21A, a top electrode pattern 25B inthe capacitor device region 21B, which is reserved for the capacitor tobe formed therein, and a gate electrode 25C of the p-channel MOStransistor or n-channel MOS transistor, which is to be formed in thelogic device region 21C.

Further, as a result of this patterning process, the thermal oxide film24 is patterned in conformity with the top electrode pattern 23B,resulting in formation of a capacitor insulation film 24B.

Furthermore, in the logic device region 21C, the thermal oxide film 24is patterned right underneath the gate electrode 25C, and as a result,there is formed a gate insulation film 24C in conformity with the gateelectrode 25C. Similarly, in the resistance region 21A, too, the thermaloxide film 24 is patterned to the shape conformal to the resistorpatterns 25A, resulting in formation of insulation film patterns 24A.

From the viewpoint of forming the resistor of high precision whileeliminating the effect of stray capacitance caused by the substrate, itis preferable to form the resistor patterns 25A on the insulation film23A as shown in FIG. 8F.

Next, in the step of FIG. 8G, the structure of FIG. 8F is annealed forthe duration of 1 second to 10 seconds at the temperature of 1000°C.-1100° C., and with this, B, which has been introduced in the step ofFIG. 8E, undergoes diffusion into the top electrode pattern 25B. Asexplained already with reference to FIG. 3, the top electrode pattern25B is given a high electric conductivity for the entire parts thereofeven when the initial silicon film is formed of undoped polysilicon oramorphous silicon, and the problem of depletion of the polysilicon topelectrode and an associated problem of a decrease of the capacitance ofcapacitor are resolved.

Further, in the case where the resistor pattern 25A, the top electrodepattern 25B and the gate electrode pattern 25C are formed by anamorphous silicon film in the step of FIG. 8F, crystallization occurs inthese silicon layers in the step of FIG. 8G as a result of the thermalannealing process, and this crystallization results in conversion of theamorphous silicon film into a polysilicon film. Furthermore, in the casewhere the resistor pattern 25A, the top electrode pattern 25B and thegate electrode pattern 25C are formed of a polysilicon film, graingrowth occurs in the polysilicon films, and the polysilicon films areconverted into a polysilicon film of more coarse grain texture.

In the step of FIG. 8G, no transistor of miniature scale is formed inthe logic device region 21C, and thus, there arises no problem ofdegradation of transistor characteristics formed in the logic deviceregion 21C, even when the thermal annealing process is conducted in thestep of FIG. 8G.

Next, in the step of FIG. 8H, a resist pattern R2 is formed on thestructure of FIG. 8G in order to expose only the resistor device region21A, and ion implantation of B+, or an n-type impurity element such asAs+ or P+ if necessary, is conducted into the resistor patterns 25Awhile using the resist pattern R2 as a mask. With this, the resistorpatterns 25A are given the desired conductivity and desired resistancevalue. For example, it is possible to provide the desired conductivityand resistance value to the resistor patterns 25A by introducing B+ asthe impurity element by an ion implantation process conducted under theacceleration voltage of 8 keV and the dose of 4.5×10¹⁵ cm².

Next, in the step of FIG. 8I, the resist pattern R2 is removed, and aresist pattern R3 is formed in order to expose only the logic deviceregion 21C. Further, B+ is introduced into the silicon substrate 21 andthe polysilicon gate electrode 25C by an ion implantation process in thecase of forming a p-channel MOS transistor in the logic device region21C. In the case of forming an n-channel MOS transistor in the logicdevice region 21C, As+ or P+ is introduced into the silicon substrate 21and also to the polysilicon gate electrode 25C by an ion implantationprocess. With this, there are formed lightly doped drain (LDD) regions21 a and 21 b of p-type for example in the silicon substrate incorrespondence to the conductivity type of the introduced impurityelement respectively at a first side and a second side opposite to thefirst side of the gate electrode 25C.

Further, in the step of FIG. 8J, sidewall insulation films 26 are formedat respective sidewall surfaces of the gate electrode 25C, and a resistpattern R4 is formed on the silicon substrate 21 in order to expose onlythe logic device region 21C. Further, source and drain regions 21 c and21 d are formed at respective outer sides of the LDD regions 21 a and 21b by introducing B+ into the device region 21C in the case of forming ap-channel MOS transistor in the device region 21C, or by introducing As+or P+ into the device region 21C in the case of forming an n-channel MOStransistor in the device region 21C, while using the gate electrode 25Cand the sidewall insulation films 26 as a self-alignment mask. Duringthis process, the polysilicon gate electrode 25C is doped to a highconcentration level of p-type or n-type.

In the step of FIG. 8K, silicide layers 27 of NiSi or CoSi₂ are formedon the surface of the polysilicon gate electrode 25C, the surface of thesource region 21 c and the surface of the drain region 21 b, which areexposed in the logic device region 21C, by way of a salicide process,for example. With this, the semiconductor device is completed. While notillustrated, such a silicide layer may also be formed on the topelectrode 25B.

Thus, with the present embodiment, the present invention provides amethod for fabricating a semiconductor device, including the steps of:forming the first trench part 22B in the capacitor device region 21B ofthe semiconductor substrate 21, forming the capacitor insulation film 24on the sidewall surface of the first trench part 22B, forming thesemiconductor film 25 to cover the first trench part 22B, the resistorpart of the semiconductor substrate 21 and further the logic deviceregion 21C of the semiconductor substrate 21, introducing a firstimpurity element into the semiconductor film 25 formed in the firsttrench part, patterning the semiconductor film to form the top electrodepattern 25B in the capacitor device region 21B, the resistor pattern 25Ain the resistor device region 21A and the gate electrode pattern 25C inthe logic device region 21C, annealing the semiconductor substrate, andintroducing a second impurity element into the resistor pattern 25A.

According to the present invention, the silicon top electrode pattern25B is annealed after the first impurity element is introducedselectively by the ion implantation process. Thereby, it becomespossible that the first impurity element reaches the part of the silicontop electrode pattern 25B covering the innermost bottom of the trenchpart 22B, and the problem of depletion of the polysilicon top electrodein the capacitor formed in the capacitor device region 21B, aspreviously explained with reference to FIG. 3, is eliminated. Thus, itbecomes possible to effectively compensate for the decrease ofcapacitance caused with such depletion.

Because the ion implantation process into the resistor device region 21Ais conducted after the thermal annealing process for causing thediffusion of the impurity element in the polysilicon top electrodepattern 25B, there is no problem that the impurity element escaping fromthe resistor pattern 25A, and the problem of variation of the resistancevalue of the polysilicon resistor pattern 25A, caused as a result of thethermal annealing process as explained with reference to FIG. 5A, can besuccessfully avoided. Reference should be made to the explanation madepreviously with reference to FIG. 5B.

Further, with the present embodiment, it should be noted that patterningprocess for forming the resistor pattern, the top electrode pattern 25Band the gate electrode pattern 25C is conducted prior to the annealingstep of FIG. 8G. Thus, the foregoing patterning process can be conductedconveniently without changing the patterning recipe used in usualpatterning process of a polysilicon film or an amorphous silicon film.

Preferably, the capacitor insulation film 24 has an increased filmthickness in the part 23B covering the bottom surface of the trench part22B as compared with the film thickness in the part 24B covering thesidewall surface of the trench part 22B. With such a construction, itbecomes possible to effectively suppress the leakage current at thebottom of the trench part 22B.

Preferably, the semiconductor substrate 21 is made of a siliconsubstrate, and the part 24B of the capacitor insulation film 24 coveringthe sidewall surface of the trench part is made of a thermal oxide filmformed by a thermal oxidation process of the silicon substrate 21.

Preferably, B having a large diffusion coefficient is used for the firstand second impurity elements. Further, the effect of suppressing thevariation of resistance value of the resistor pattern appearsconspicuous in the case where the first and second impurity elements areformed of B.

In the resistor device region 21A, another trench part 22A is formed,and the resistors 25A are formed on the insulation film 23A filling thisother trench part. Preferably, the trench part 223 and the other trenchpart 22A are formed on the semiconductor substrate simultaneously. As aresult of such a construction, there is no longer the need of formingthe trench part 22A, the trench part 22B, the insulation film patterns23B and 23A with separate processes, and the formation process issimplified.

Preferably, the capacitor insulation film 24 is formed by the steps of:depositing a CVD insulation film on the semiconductor substrate 21 so asto fill the trench part 22B and the other trench part 22A, removing theCVD insulation film on the surface of the semiconductor substrate by achemical mechanical polishing process, removing the CVD film filling thetrench part in the capacitor device region except for the bottom part byan etch-back process, and thermally oxidizing the silicon substrateafter the etch-back process. The capacitor insulation film thus formedcan be formed to have a greater film thickness in the part covering thebottom of the trench part in the capacitor device region 21B as comparedwith the part covering the sidewall surface of the trench part. Withthis, it becomes possible to suppress the occurrence of leakage currentat such a bottom part.

The logic device region 21C is defined by a device isolation region,wherein the device isolation region includes the device isolation trench22C formed in the semiconductor substrate 21 and the device isolationinsulation film 23 filling the device isolation trench 22C. The deviceisolation trench 22C is formed at the same time as the trench part 223is formed. Furthermore, the other trench part 22A, and the deviceisolation insulation film 23C are formed at the same time as theinsulation film 23A fills the other trench part 22A. With such aprocess, the steps for separately forming the device isolation trench22C and the device isolation film 23C are no longer needed, and thefabrication process of the semiconductor device is simplified.

Preferably, the semiconductor substrate 21 is a silicon substrate. It isalso preferable that the part of the capacitor insulation film 24covering the sidewall surface of the trench part 22B and the gateinsulation film 24C are formed simultaneously by the thermal oxidationprocess applied to the surface of the silicon substrate 21. With such aprocess, there is no longer the need of separately forming the gateinsulation film 24C and the capacitor insulation film 24, and thefabrication process of the semiconductor device is simplified.

Preferably, the gate electrode pattern 25C is formed at the same timethat the silicon top electrode pattern 25B and the silicon resistorpattern 25A are formed as a result of patterning of the silicon film 25.With such a construction, there is no longer the need for forming thegate electrode 25C with a process separate from the forming of thesilicon top electrode pattern 25B or forming of the silicon resistorpattern 25A, and the fabrication process of the semiconductor device issimplified.

Further, by conducting an ion implantation process of a third impurityelement in the logic device region 21C while using the gate electrodepattern 25C as a mask, the diffusion regions 21 a and 21 b, and furtherthe diffusion regions 21C and 21 d, are formed respectively at a firstside and a second side opposite to the first side of the gate electrodepattern 25C. Thus, it becomes possible to form a p-channel MOStransistor or an n-channel MOS transistor, or a complementarymetal-oxide semiconductor (CMOS) device including a p-channel MOStransistor and an n-channel MOS transistor, in the logic device region21C.

It is preferable that the trench part 22B has a width of 0.25 μm or lessat the surface of the semiconductor substrate 21 and a depth exceeding0.2 μm. The effect of the present invention appears particularlyconspicuous in the case of forming a capacitor element in such aminiaturized trench part having a large aspect ratio.

In the present embodiment, it is also possible to convert the thermaloxide film 24 into an oxynitride film by carrying out a plasmanitridation processing immediately after the step of FIG. 8C. As aresult of such a construction and process, it becomes possible tofurther increase the capacitance of the capacitor, and the oxide filmequivalent thickness of the gate insulation film can be reduced for thep-channel MOS transistor or the n-channel MOS transistor formed in thelogic device region 21C. Because of this, it becomes possible to operatethese transistors with higher speed by using a shorter gate length.Further, in the step of FIG. 8C, it is also possible to form a plasmaoxide film or plasma oxynitride film directly on the surface of thesilicon substrate 21 in place of the thermal oxide film 24.

FIGS. 9A-9K are diagrams showing the process of fabricating asemiconductor device according to a second embodiment of the presentinvention.

Referring to FIG. 9A, there are defined a resistor device region 41A, acapacitor device region 41B and a logic device region 41C on a siliconsubstrate 41, and trenches 42A, 42B and 42C are formed simultaneously inthe resistor device region 41A, the capacitor device region 41B and thelogic device region 41C, respectively.

In one example, the trench 42B and the device isolation trench 42C areformed, in accordance with the design rule, such that the trench part42B and the device isolation trench 42C have a width of 0.1 μm at thesurface of the silicon substrate 41 and a depth of 0.2 μm.

The trench parts 42A and 42B and the device isolation trench 42C arefilled respectively with CVD oxide films 43A, 43B and 43C, whereinexcessive silicon oxide film at the surface of the silicon substrate 41is removed by a chemical mechanical polishing (CMP) process.

Next, in the step of FIG. 9B, the resistor device region 41A and thelogic device region 41C are covered with a resist pattern (not shown),and an etch-back process is conducted for the exposed capacitor deviceregion 41B in order to etch back the silicon oxide film therein by a dryetching process. With this, the CVD oxide film 43B is receded at thetrench part 42B until a CVD oxide film 43B is left at the bottom of thetrench part 42B with a thickness of 70 nm, for example. Further, in thisstep, ion implantation of a p-type element such as B+, or if necessaryan n-type element such as As+ or P+, is conducted for the capacitordevice region 41B, and with this, a conductive well 41W is formed as thebottom electrode of the capacitor. In the explanation below, furtherdescription of the conductive well 21W is omitted.

Next, in the step of FIG. 9C, a thermal oxidation process is performedon the structure of FIG. 9B in an oxygen ambient at the temperature of1000° C., for example, and with this, a thermal oxide film 44 is formedon the surface of the silicon substrate 41, including the exposedsidewall surface of the trench part 42B with a thickness of 2 nm, forexample.

Next, in the step of FIG. 9D, an undoped polysilicon film 45 isdeposited on the structure of FIG. 9C at the substrate temperature of605° C. in order to fill the trench part 42B typically with thethickness of 105 nm. In place of the polysilicon film 45, it is alsopossible to deposit an amorphous silicon film. In this case, thesubstrate temperature is set to 530° C., for example, in the depositionstep. Hereinafter, the film 45 will be designated as “silicon film”.

Next, in the step of FIG. 9E, a resist pattern R11 is formed exposingonly the capacitor device region 41B on the structure of FIG. 9D, and anion implantation of B+ is performed on the silicon film 45 while usingthe resist pattern R11 as a mask under the acceleration voltage of 4 keVwith the dose of 5.5×10¹⁵ cm⁻², for example. For the purposes of thediffusion process, which is explained later with reference to FIG. 9F,it is preferable to use B+ having a large diffusion coefficient in thisstep of FIG. 9E for the impurity element.

Next, in the step of FIG. 9F, the structure of FIG. 9E is annealed forthe duration of several seconds to about 10 seconds at the temperatureof 1000-1100° C., and with this, B undergoes diffusion into the topelectrode pattern 45B. As explained already with reference to FIG. 3,the entire silicon film 45 is given a high electric conductivity, evenwhen the initial silicon film is formed of undoped polysilicon oramorphous silicon, and the problem of depletion of the polysilicon topelectrode and the associated problem of a decrease of capacitance of thecapacitor are reduced or eliminated. Further, in the step of FIG. 9F,crystallization occurs in the silicon film 45, in the case where thesilicon film 45 is formed as an amorphous silicon film in the step ofFIG. 9E, which results in a conversion of the amorphous silicon filminto polysilicon film. Furthermore, in the case where the silicon film45 is formed of a polysilicon film, grain growth occurs in thepolysilicon film 45, which results in conversion of the polysilicon film45 into a polysilicon film of more coarse texture.

In the step of FIG. 9F, no transistor of miniature scale is formed inthe logic device region 41C, and thus, there arises no problem ofdegradation of transistor characteristics formed in the logic deviceregion 41C, even when the thermal annealing process is conducted in thestep of FIG. 9F.

Next, in the step of FIG. 9G, the silicon film 45 of polysilicon oramorphous silicon of the structure of FIG. 9E is patterned, and withthis, resistor patterns 45A are formed in the resistor device region41A, a top electrode pattern 45B in the capacitor device region 41B,which is reserved for the capacitor to be formed therein. Furthermore, agate electrode 45C of the p-channel MOS transistor or an n-channel MOStransistor is formed in the logic device region 41C. As a result of thispatterning process, the thermal oxide film 44 is patterned in conformitywith the top electrode pattern 45B, resulting in formation of acapacitor insulation film 44B. In the logic device region 21C, thethermal oxide film 44 is patterned right underneath the gate electrode45C, and as a result, a gate insulation film 44C is formed in conformitywith the gate electrode 45C. In the resistance region 41A, the thermaloxide film 44 is patterned to the shape that conforms with the resistorpatterns 45A, resulting in formation of insulation film patterns 44A.

Next, in the step of FIG. 9H, a resist pattern R12 is formed on thestructure of FIG. 9G in order to expose only the resistor device region41A. Ion implantation of B+, or an n-type impurity element such as As+or P+ if necessary, is performed on the resistor patterns 45A whileusing the resist pattern R12 as a mask. With this, the resistor patterns45A are given the desired conductivity and desired resistance value. Forexample, it is possible to provide the desired conductivity andresistance value to the resistor patterns 25A by introducing B+ as theimpurity element by an ion implantation process conducted under theacceleration voltage of 8 keV and the dose of 4.5×10¹⁵ cm⁻².

Next, in the step of FIG. 9I, the resist pattern R12 is removed, and aresist pattern R13 is formed in order to expose only the logic deviceregion 21C. Further, B+ is introduced into the silicon substrate 41 andthe polysilicon gate electrode 45C by an ion implantation process in thecase where a p-channel MOS transistor is formed in the logic deviceregion 41C. In the case of forming an n-channel MOS transistor in thelogic device region 41C, As+ or P+ is introduced into the siliconsubstrate 41 and into the polysilicon gate electrode 45C by an ionimplantation process. With this, LDD regions 41 a and 41 b of p-type areformed, for example, in the silicon substrate corresponding to theconductivity type of the introduced impurity element at a first side anda second side opposite to the first side of the gate electrode 45C.

Further, in the step of FIG. 9J, sidewall insulation films 46 are formedat respective sidewall surfaces of the gate electrode 45C, and a resistpattern R14 is formed on the silicon substrate 41 to expose only thelogic device region 41C. In addition, source and drain regions 41 c and41 d are formed at respective outer sides of the LDD regions 41 a and 41b by introducing B+ into the device region 41C in the case of forming ap-channel MOS transistor in the device region 41C, or by introducing As+or P+ into the device region 41C in the case of forming an n-channel MOStransistor in the device region 41C, while using the gate electrode 45Cand the sidewall insulation films 46 as a self-alignment mask. Duringthis process, the polysilicon gate electrode 45C is doped to a highconcentration level of p-type or n-type.

Further, in the step of FIG. 9K, silicide layers 47 of NiSi or CoSi₂ areformed on the surface of the polysilicon gate electrode 45C, the surfaceof the source region 41 c and the surface of the drain region 41 b,which surfaces are exposed in the logic device region 41C, by way of asalicide process, for example. With this, the semiconductor device iscompleted. While not illustrated, such a silicide layer may also beformed also on the top electrode 45B.

Thus, the present embodiment of the invention provides a fabricationprocess of a semiconductor device, comprising the steps of: forming thefirst trench part 42B in the capacitor device region 41B on thesemiconductor substrate 41, forming the capacitor insulation film 44 onthe sidewall surface of the first trench part 42B, depositing thesemiconductor film 45 to cover the first trench part 42B, the resistordevice region of the semiconductor substrate and the logic device region41C of the semiconductor substrate, introducing the first impurityelement into the semiconductor film 45 in the capacitor device region41B, annealing the semiconductor substrate 41, patterning thesemiconductor film 45 to form the top electrode pattern 45B in thecapacitor device region 41B, the resistor patterns 45A in the resistordevice region 41A, and the gate electrode pattern 45C in the logicdevice region 41C, and introducing the second impurity element into theresistor patterns 45A.

According to the present invention, the silicon top electrode pattern45B is annealed after the first impurity element is selectivelyintroduced by the ion implantation process. Because of this, it becomespossible that the first impurity element reaches the part of the silicontop electrode pattern 45B covering the innermost bottom of the trenchpart 42B, and the problem of depletion of the polysilicon top electrodein the capacitor formed in the capacitor device region 41B (as explainedwith reference to FIG. 3) is eliminated. Thus, it becomes possible toeffectively compensate for the decrease of capacitance caused with suchdepletion. As a result, it should be noted that, because the ionimplantation process into the resistor device region 41A is conductedafter the thermal annealing process for causing the diffusion of theimpurity element in the polysilicon top electrode pattern 45B, theimpurity element does not escape from the resistor patterns 45A.Therefore, the problem of variation of the resistance value of thepolysilicon patterns 45A of the resistor caused by the thermal annealingprocess (as explained with reference to FIG. 5A) can be successfullyavoided.

Preferably, the capacitor insulation film 44 has an increased filmthickness in the part 43B covering the bottom surface of the trench part42B as compared with the film thickness in the part 44B covering thesidewall surface of the trench part 42B. With such a construction, itbecomes possible to effectively suppress the leakage current at thebottom of the trench part 42B.

Preferably, the semiconductor substrate 41 is made of a siliconsubstrate, and the part 44B of the capacitor insulation film 44 coveringthe sidewall surface of the trench part is made of a thermal oxide filmformed by a thermal oxidation process of the silicon substrate 41.

Preferably, B having a large diffusion coefficient is used for the firstand second impurity elements. Further, the effect of suppressing thevariation of resistance value of the resistor pattern appearsconspicuous in the case the first and second impurity elements areformed of B.

In the resistor device region 41A, there is formed another trench part42A, and the resistors 45A are formed on the insulation film 43A fillingthis other trench part. Preferably, the trench part 42B and the othertrench part 42A are formed on the semiconductor substratesimultaneously. As a result of such a construction, there is no longerthe need of forming the trench part 42A, the trench part 42B, theinsulation film patterns 43B and 43A with separate processes, and theformation process is simplified.

Preferably, the capacitor insulation film 44 is formed by the steps of:depositing a CVD insulation film on the semiconductor substrate 41 tofill the trench part 42B and the other trench part 42A, removing the CVDinsulation film on the surface of the semiconductor substrate by achemical mechanical polishing process, removing the CVD film filling thetrench part in the capacitor device region except for the bottom part byan etch-back process, and thermally oxidizing the silicon substrateafter the etch-back process. The capacitor insulation film can be formedto have a greater film thickness in the part covering the bottom of thetrench part in the capacitor device region 41B as compared with the filmthickness in the part covering the sidewall surface of the trench part.With this, it becomes possible to suppress any leakage current at such abottom part.

The logic device region 41C is defined by a device isolation region,wherein the device isolation region includes the device isolation trench42C formed in the semiconductor substrate 41 and the device isolationinsulation film 43 filling the device isolation trench. There, thedevice isolation trench 42C is formed at the same time as the formationof the trench part 42B and the other trench part 42A, and the deviceisolation insulation film 43C is formed at the same time as theformation of the insulation film 43A filling the other trench part 42A.With such processes, the steps for separately forming the deviceisolation trench 42C and the device isolation film 43C are no longerneeded, and the fabrication process of the semiconductor device issimplified.

Preferably, the semiconductor substrate 41 is a silicon substrate.Further, it is preferable that the part of the capacitor insulation film44 covering the sidewall surface of the trench part 42B and the gateinsulation film 44C are formed simultaneously by the thermal oxidationprocess applied to the surface of the silicon substrate 41. With such aprocess, there is no longer the need of separately forming the gateinsulation film 44C and the capacitor insulation film 44, and thefabrication process of the semiconductor device is simplified.

Preferably, the gate electrode pattern 45C is formed at the same time asthe silicon top electrode pattern 45B and the silicon resistor pattern45A as a result of patterning of the silicon film 45. With such aconstruction, there is no longer the need for forming the gate electrode45C with a process separate from forming of the silicon top electrodepattern 25B or of the silicon resistor pattern 45A, and the fabricationprocess of the semiconductor device is simplified.

Further, by conducting an ion implantation process of a third impurityelement in the logic device region 41C while using the gate electrodepattern 45C as a mask, the diffusion regions 41 a and 41 b, and thediffusion regions 41 c and 41 d, are formed at a first side and a secondside opposite to the first side of the gate electrode pattern 45C. Thus,it becomes possible to form a p-channel MOS transistor or an n-channelMOS transistor, or a CMOS device that includes a p-channel MOStransistor and an n-channel MOS transistor, in the logic device region41C.

It is preferable that the trench part 42B has a width of 0.25 μm or lessat the surface of the semiconductor substrate 41 and a depth exceeding0.2 μm. The present invention appears particularly effective in the caseof forming a capacitor in such a miniaturized trench part having a largeaspect ratio.

In the present embodiment, it is also possible to convert the thermaloxide film 44 into an oxynitride film by carrying out a plasmanitridation processing immediately after the step of FIG. 9C. As aresult of such a construction and process, it becomes possible tofurther increase the capacitance of the capacitor, and the oxide filmequivalent thickness of the gate insulation film can be reduced for thep-channel MOS transistor or the n-channel MOS transistor formed in thelogic device region 41C. Therefore, it becomes possible to operate thesetransistors at a higher speed by using a shorter gate length.Furthermore, in the step of FIG. 9C, it is also possible to form aplasma oxide film or plasma oxynitride film directly on the surface ofthe silicon substrate 41 in place of the thermal oxide film 44.

While the present invention has been explained for preferredembodiments, the present invention is not limited to such specificembodiments and various variations and modifications may be made withinthe scope of the invention described in patent claims.

1. A method of manufacturing a semiconductor device, comprising: forminga first trench in a capacitor device region of a semiconductorsubstrate; forming a capacitor insulation film over a sidewall surfaceof said first trench; forming a semiconductor film to cover said firsttrench, a resistor device region of said semiconductor substrate and alogic device region of said semiconductor substrate; introducing a firstimpurity element into said semiconductor film formed over said firsttrench; patterning said semiconductor film to form a top electrode insaid capacitor device region, a resistor in said resistor device regionand a gate electrode in said logic device region; annealing saidsemiconductor substrate; and introducing a second impurity element insaid resistor.
 2. The method as claimed in claim 1, wherein saidsemiconductor film comprises an undoped silicon film.
 3. The method asclaimed in claim 1, wherein said capacitor insulation film is formedalso over a bottom surface of said first trench, and wherein saidcapacitor insulation film over the bottom surface has a first filmthickness, and said capacitor insulation film over the sidewall surfacehas a second film thickness thinner than the first film thickness. 4.The method as claimed in claim 1, wherein said semiconductor devicecomprises a silicon substrate and said capacitor insulation film formedover said sidewall surface is a thermal oxide film.
 5. The method asclaimed in claim 1, wherein said first impurity element and said secondimpurity element are boron.
 6. The method as claimed in claim 1, whereina second trench is formed in said resistor device region in forming saidfirst trench.
 7. The method as claimed in claim 6, wherein saidcapacitor insulation film is formed by: depositing an insulation film insaid first trench and in said second trench; removing said insulationfilm in said first trench in said capacitor device region; and thermallyoxidizing said silicon substrate.
 8. The method as claimed in claim 1,wherein said resistor is formed over said insulation film in said secondtrench.
 9. The method as claimed in claim 7, wherein said logic deviceregion is defined by a device isolation region, said device isolationregion comprising a device isolation trench formed in said semiconductorsubstrate and a device isolation insulation film in said deviceisolation trench; said device isolation trench being formed in the stepsof forming said first trench and forming said second trench, said deviceisolation insulation film being deposited in said step of depositingsaid insulation film.
 10. The method as claimed in claim 1, wherein saidsemiconductor substrate comprises a silicon substrate, and wherein saidcapacitor insulation film covering said sidewall surface of said firsttrench and said gate insulation film are formed simultaneously bythermal oxidation of a surface of said silicon substrate.
 11. The methodas claimed in claim 1, wherein said gate electrode is formed bypatterning of said semiconductor film in said step of patterning saidtop electrode and said resistor.
 12. The method as claimed in claim 1,further comprising: introducing a third impurity element into saidsemiconductor substrate in said logic device region while using saidgate electrode as a mask.
 13. The method as claimed in claim 1, whereinsaid first trench has a width of 0.08 μm-0.25 μm at a surface of saidsemiconductor substrate.
 14. The method as claimed in claim 1, whereinsaid first trench has a depth of 0.2 μm-0.35 μm.
 15. A method ofmanufacturing a semiconductor device, comprising: forming a first trenchin a capacitor device region of a semiconductor substrate; forming acapacitor insulation film over a sidewall surface of said first trench;depositing a semiconductor film over said first trench, a resistordevice region of said semiconductor substrate and a logic device regionof said semiconductor substrate; introducing a first impurity elementinto said semiconductor film; annealing said semiconductor substrate;patterning said semiconductor film to form a top electrode in saidcapacitor device region, a resistor in said resistor device region and agate electrode in said logic device region; and introducing a secondimpurity element in said resistor.